Jingwei Cai

I received my Ph.D. in Computer Systems Architecture from the Institute for Interdisciplinary Information Sciences (IIIS), Tsinghua University in 2026, under the supervision of Prof. Kaisheng Ma. During my Ph.D., I worked on DNN accelerator architecture and compiler design for 2.5D/3D/wafer-scale chiplets, wafer-scale silicon photonic computing, recommendation-system acceleration, and cloud LLM inference optimization.

I am currently with the Heterogeneous Computing team at ByteDance SEED, where I study cloud AI workloads and optimize online LLM inference systems. I also develop early-stage architecture simulators and contribute to hardware-software co-design for emerging 3D DRAM and AI accelerator platforms, turning production requirements into practical system and architecture improvements.

My work connects academic research with real-world systems. I have published 7 papers, including 5 first-author papers in CCF-A computer architecture venues, and received the HPCA 2024 Distinguished Artifact Award. I have also led architecture and compiler development for multiple generations of Qiming DNN accelerators at Arctic Xiongxin, bringing research ideas into production compiler stacks and chip designs.

For more details, please see my CV. I am currently working at ByteDance SEED and remain open to exceptional opportunities where I can tackle ambitious problems and make a broader impact.

news

Dec 23, 2025

I received the Wang Dazhong Scholarship and was nominated by IIIS for Tsinghua University’s Top-Grade Scholarship.

Nov 24, 2025

I was named a 2025 ByteDance Scholar, one of 20 doctoral recipients from China and Singapore.

Apr 01, 2025

I joined the Heterogeneous Computing team at ByteDance SEED, working on workload characterization, chip co-design, and LLM inference optimization.

Jan 04, 2025

I was selected for the inaugural CAST Young Talent Support Program for Doctoral Students as IIIS’s sole recipient.

Nov 03, 2024

Our work SoMa was accepted to HPCA 2025.

selected publications

HPCA

Characterizing Cloud-Native LLM Inference at ByteDance and Exposing Optimization Challenges and Opportunities for Future AI Accelerators

Jingwei Cai, Dehao Kong , Hantao Huang , and 8 more authors

In IEEE International Symposium on High-Performance Computer Architecture, Industry Track , 2026

Bib

@inproceedings{cai2026cloudnative,
  author = {Cai, Jingwei and Kong, Dehao and Huang, Hantao and Jiang, Zishan and Ma, Zixuan and Guo, Qingyu and Zhang, Zhenxing and Shi, Guiming and Gao, Mingyu and Ma, Kaisheng and Yu, Minghui},
  title = {Characterizing Cloud-Native {LLM} Inference at {ByteDance} and Exposing Optimization Challenges and Opportunities for Future {AI} Accelerators},
  booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture, Industry Track},
  year = {2026},
}

HPCA

Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators

Jingwei Cai, Xuan Wang , Mingyu Gao , and 5 more authors

In IEEE International Symposium on High-Performance Computer Architecture , 2025

Bib

@inproceedings{cai2025soma,
  author = {Cai, Jingwei and Wang, Xuan and Gao, Mingyu and Peng, Sen and Zhu, Zijian and Wei, Yuchen and Wu, Zuotong and Ma, Kaisheng},
  title = {Identifying, Exploring, and Understanding the {DRAM} Communication Scheduling Space for {DNN} Accelerators},
  booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture},
  year = {2025},
}

DAC

Discovering and Exploiting Untapped Buffer Resources in Many-Core DNN Accelerators

Yuchen Wei , Jingwei Cai, Mingyu Gao , and 4 more authors

In Design Automation Conference , 2025

Bib

@inproceedings{wei2025buffer,
  author = {Wei, Yuchen and Cai, Jingwei and Gao, Mingyu and Peng, Sen and Wu, Zuotong and Shi, Guiming and Ma, Kaisheng},
  title = {Discovering and Exploiting Untapped Buffer Resources in Many-Core {DNN} Accelerators},
  booktitle = {Design Automation Conference},
  year = {2025},
}

HPCA

Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators

Jingwei Cai, Zuotong Wu , Sen Peng , and 5 more authors

In IEEE International Symposium on High-Performance Computer Architecture , 2024

Bib

@inproceedings{cai2024gemini,
  author = {Cai, Jingwei and Wu, Zuotong and Peng, Sen and Wei, Yuchen and Tan, Zhanhong and Shi, Guiming and Gao, Mingyu and Ma, Kaisheng},
  title = {Gemini: Mapping and Architecture Co-exploration for Large-scale {DNN} Chiplet Accelerators},
  booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture},
  pages = {156--171},
  publisher = {{IEEE}},
  year = {2024},
  url = {https://doi.org/10.1109/HPCA57654.2024.00022},
  doi = {10.1109/HPCA57654.2024.00022},
}

ISCA

Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators

Jingwei Cai, Yuchen Wei , Zuotong Wu , and 2 more authors

In Proceedings of the 50th Annual International Symposium on Computer Architecture , 2023

Bib

@inproceedings{cai2023set,
  author = {Cai, Jingwei and Wei, Yuchen and Wu, Zuotong and Peng, Sen and Ma, Kaisheng},
  title = {Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators},
  booktitle = {Proceedings of the 50th Annual International Symposium on Computer Architecture},
  pages = {13:1--13:17},
  publisher = {{ACM}},
  year = {2023},
  url = {https://doi.org/10.1145/3579371.3589048},
  doi = {10.1145/3579371.3589048},
}